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Features
* High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture
- 54 Powerful Instructions - Most Single Clock Cycle Execution - 16 x 8 General Purpose Working Registers - Fully Static Operation - Up to 12 MIPS Throughput at 12 MHz Non-volatile Program and Data Memories - 2K Bytes of In-System Programmable Flash Program Memory - 128 Bytes Internal SRAM - Flash Write/Erase Cycles: 10,000 - Data Retention: 20 Years at 85oC / 100 Years at 25oC Peripheral Features - One 8-bit Timer/Counter with Two PWM Channels - One 16-bit Timer/Counter with Two PWM Channels - 10-bit Analog to Digital Converter * 8 Single-Ended Channels - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator - Master/Slave SPI Serial Interface - Slave TWI Serial Interface Special Microcontroller Features - In-System Programmable - External and Internal Interrupt Sources - Low Power Idle, ADC Noise Reduction, Stand-by and Power-down Modes - Enhanced Power-on Reset Circuit - Internal Calibrated Oscillator I/O and Packages - 14-pin SOIC/TSSOP: 12 Programmable I/O Lines - 15-pad UFBGA: 12 Programmable I/O Lines - 20-pad QFN/MLF: 12 Programmable I/O Lines Operating Voltage: - 1.8 - 5.5V Programming Voltage: - 5V Speed Grade - 0 - 4 MHz @ 1.8 - 5.5V - 0 - 8 MHz @ 2.7 - 5.5V - 0 - 12 MHz @ 4.5 - 5.5V Industrial Temperature Range Low Power Consumption - Active Mode: * 200 A at 1 MHz and 1.8V - Idle Mode: * 25 A at 1 MHz and 1.8V - Power-down Mode: * < 0.1 A at 1.8V
*
*
8-bit Microcontroller with 2K Bytes In-System Programmable Flash ATtiny20 Preliminary Summary
*
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Rev. 8235AS-AVR-03/10
1. Pin Configurations
Figure 1-1. Pinout of ATtiny20
SOIC/TSSOP
VCC (PCINT8/TPICLK/T0/CLKI) PB0 (PCINT9/TPIDATA/MOSI/SDA/OC1A) PB1 (PCINT11/RESET) PB3 (PCINT10/INT0/MISO/OC1B/OC0A/CKOUT) PB2 (PCINT7/SCL/SCK/T1/ICP1/OC0B/ADC7) PA7 (PCINT6/SS/ADC6) PA6 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND PA0 (ADC0/PCINT0) PA1 (ADC1/AIN0/PCINT1) PA2 (ADC2/AIN1/PCINT2) PA3 (ADC3/PCINT3) PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5)
VQFN
Pin 16: PA6 (ADC6/SS/PCINT6) Pin 17: PA5 (ADC5/PCINT5) PA7 (ADC7/OC0B/ICP1/T1/SCL/SCK/PCINT7) PB2 (CKOUT/OC0A/OC1B/MISO/INT0/PCINT10) PB3 (RESET/PCINT11) PB1 (OC1A/SDA/MOSI/TPIDATA/PCINT9) PB0 (CLKI/T0/TPICLK/PCINT8)
NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect
Table 1-1.
A B C D
UFBGA - Pinout ATtiny20.
1 2 PA5 PA4 PA3 PA0 PA7 PA2 GND 3 PA6 PB1 PA1 GND 4 PB2 PB3 PB0 VCC
1.1
1.1.1
Pin Description
VCC Supply voltage.
1.1.2
GND Ground.
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ATtiny20
8235AS-AVR-03/10
DNC DNC GND VCC DNC
6 7 8 9 10
(PCINT4/ADC4) PA4 (PCINT3/ADC3) PA3 (PCINT2/AIN1/ADC2) PA2 (PCINT1/AIN0/ADC1) PA1 (PCINT0/ADC0) PA0
1 2 3 4 5
20 19 18 17 16
DNC DNC DNC PA5 PA6
15 14 13 12 11
ATtiny20
1.1.3 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 21-4 on page 176. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. 1.1.4 Port A (PA7:PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has alternate functions as analog inputs for the ADC, analog comparator and pin change interrupt as described in "Alternate Port Functions" on page 49. 1.1.5 Port B (PB3:PB0) Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (`0') RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. The port also serves the functions of various special features of the ATtiny20, as listed on page 39.
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8235AS-AVR-03/10
2. Overview
ATtiny20 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny20 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. Block Diagram
VCC RESET
PROGRAMMING LOGIC
PROGRAM COUNTER
INTERNAL OSCILLATOR
CALIBRATED OSCILLATOR
PROGRAM FLASH
STACK POINTER
WATCHDOG TIMER
TIMING AND CONTROL
INSTRUCTION REGISTER
SRAM
RESET FLAG REGISTER
INSTRUCTION DECODER
INTERRUPT UNIT
MCU STATUS REGISTER
CONTROL LINES
GENERAL PURPOSE REGISTERS
X Y Z
TIMER/ COUNTER0
TIMER/ COUNTER1
ALU
SPI
ANALOG COMPARATOR
ISP INTERFACE
STATUS REGISTER
TWI
ADC
8-BIT DATA BUS
DATA REGISTER PORT A
DIRECTION REG. PORT A
DATA REGISTER PORT B
DIRECTION REG. PORT B
DRIVERS PORT A
DRIVERS PORT B
PA7:0
GND
PB3:0
The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle.
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ATtiny20
The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny20 provides the following features: 2K byte of In-System Programmable Flash, 128 bytes of SRAM, twelve general purpose I/O lines, 16 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 16-bit Timer/Counter with two PWM channels, Internal and External Interrupts, an eight-channel, 10-bit ADC, a programmable Watchdog Timer with internal oscillator, a slave two-wire interface, a master/slave serial peripheral interface, an internal calibrated oscillator, and four software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip functions are disabled until the next interrupt or hardware reset. In Standby mode, the oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. The device is manufactured using Atmel's high density non-volatile memory technology. The onchip, in-system programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. The ATtiny20 AVR is supported by a suite of program and system development tools, including macro assemblers and evaluation kits.
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3. General Information
3.1 Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
3.3
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C.
3.4
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device has been characterized.
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ATtiny20
4. Register Summary
Address
0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39 0x38 0x37 0x36 0x35 0x34 0x33 0x32 0x31 0x30 0x2F 0x2E 0x2D 0x2C 0x2B 0x2A 0x29 0x28 0x27 0x26 0x25 0x24 0x23 0x22 0x21 0x20 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
Name
SREG SPH SPL CCP RSTFLR MCUCR OSCCAL Reserved CLKMSR CLKPSR PRR QTCSR NVMCMD NVMCSR WDTCSR SPCR SPSR SPDR TWSCRA TWSCRB TWSSRA TWSA TWSAM TWSD GTCCR TIMSK TIFR TCCR1A TCCR1B TCCR1C TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR0A TCCR0B TCNT0 OCR0A OCR0B ACSRA ACSRB ADCSRA ADCSRB ADMUX ADCH ADCL DIDR0 GIMSK GIFR PCMSK1 PCMSK0 PORTCR PUEB PORTB DDRB PINB PUEA PORTA DDRA PINA
Bit 7
I
Bit 6
T
Bit 5
H
Bit 4
S
Bit 3
V
Bit 2
N
Bit 1
Z
Bit 0
C
Page
Page 14 Page 13 Page 13 Page 13
Stack Pointer High Byte Stack Pointer Low Byte CPU Change Protection Byte - ICSC01 - - - - - NVMBSY WDIF SPIE SPIF TWSHE - TWDIF - ICSC00 - - - - - - WDIE SPE WCOL - - TWASIF - WDP3 DORD - TWDIE - TWCH - - MSTR - TWASIE - TWRA - - - - - - - BODS - - - PRTWI WDRF SM2 - - CLKPS3 PRSPI BORF SM1 - - CLKPS2 PRTIM1 EXTRF SM0 - CLKMS1 CLKPS1 PRTIM0 PORF SE - CLKMS0 CLKPS0 PRADC
Page 37 Pages 28, 41 Page 23 Page 22 Page 22 Page 29 Page 152 Page 171
Oscillator Calibration Byte
QTouch Control and Status Register NVM Command - WDE CPOL - TWEN - TWC - WDP2 CPHA - TWSIE TWAA TWBE - WDP1 SPR1 SSPS TWPME TWDIR - WDP0 SPR0 SPI2X TWSME TWAS
Page 172 Page 35 Page 136 Page 138 Page 138 Page 147 Page 148 Page 149 Page 150 Page 151 Page 151
SPI Data Register TWCMD[1.0]
TWI Slave Address Register TWI Slave Address Mask Register TWI Slave Data Register TSM ICE1 ICF1 COM1A1 ICNC1 FOC1A - - - COM1A0 ICES1 FOC1B - OCIE1B OCF1B COM1B1 - - - OCIE1A OCF1A COM1B0 WGM13 - - TOIE1 TOV1 - WGM12 - - OCIE0B OCF0B - CS12 - - OCIE0A OCF0A WGM11 CS11 - PSR TOIE0 TOV0 WGM10 CS10 -
Page 108 Pages 76, 104 Pages 76, 105 Page 99 Page 101 Page 102 Page 103 Page 103 Page 103 Page 103 Page 103 Page 103 Page 104 Page 104
Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Compare Register A High Byte Timer/Counter1 - Compare Register A Low Byte Timer/Counter1 - Compare Register B High Byte Timer/Counter1 - Compare Register B Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte COM0A1 FOC0A COM0A0 FOC0B COM0B1 - COM0B0 - - WGM02 - CS02 WGM01 CS01 WGM00 CS00
Page 71 Page 74 Page 75 Page 75 Page 76
Timer/Counter0 - Counter Register Timer/Counter0 - Compare Register A Timer/Counter0 - Compare Register B ACD HSEL ADEN VDEN - ACBG HLEV ADSC VDPD REFS ACO ACLP ADATE - REFEN ACI - ADIF - ADC0EN ACIE ACCE ADIE ADLAR MUX3 ACIC ACME ADPS2 ADTS2 MUX2 ACIS1 ACIRS1 ADPS1 ADTS1 MUX1 ACIS0 ACIRS0 ADPS0 ADTS0 MUX0
Page 110 Page 111 Page 127 Page 128 Page 125 Page 126 Page 126
ADC Conversion Result - High Byte ADC Conversion Result - Low Byte ADC7D - - - PCINT7 - - - - - PUEA7 PORTA7 DDRA7 PINA7 ADC6D - - - PCINT6 - - - - - PUEA6 PORTA6 DDRA6 PINA6 ADC5D PCIE1 PCIF1 - PCINT5 - - - - - PUEA5 PORTA5 DDRA5 PINA5 ADC4D PCIE0 PCIF0 - PCINT4 - - - - - PUEA4 PORTA4 DDRA4 PINA4 ADC3D - - PCINT11 PCINT3 - PUEB3 PORTB3 DDRB3 PINB3 PUEA3 PORTA3 DDRA3 PINA3 ADC2D - - PCINT10 PCINT2 - PUEB2 PORTB2 DDRB2 PINB2 PUEA2 PORTA2 DDRA2 PINA2 ADC1D - - PCINT9 PCINT1 BBMB PUEB1 PORTB1 DDRB1 PINB1 PUEA1 PORTA1 DDRA1 PINA1 ADC0D INT0 INTF0 PCINT8 PCINT0 BBMA PUEB0 PORTB0 DDRB0 PINB0 PUEA0 PORTA0 DDRA0 PINA0
Page 129 Page 41 Page 42 Page 43 Page 43 Page 58 Page 58 Page 59 Page 59 Page 59 Page 58 Page 58 Page 58 Page 58
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8235AS-AVR-03/10
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
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ATtiny20
5. Instruction Set Summary
Mnemonics
ADD ADC SUB SUBI SBC SBCI AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID LSL LSR ROL ROR ASR SWAP BSET Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b A, b A, b s, k s, k k k k k k k k k k k k k k k k k k k Rd Rd Rd Rd Rd Rd s k
Operands
Rd, Rr Rd, Rr Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add without Carry Add with Carry Subtract without Carry Subtract Immediate Subtract with Carry
Description
Rd Rd + Rr
Operation
Flags
Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,C,N,V,S Z,C,N,V,S,H Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S None None None None None None I None Z, C,N,V,S,H Z, C,N,V,S,H Z, C,N,V,S,H None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V,H Z,C,N,V Z,C,N,V,H Z,C,N,V Z,C,N,V None SREG(s)
#Clocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3/4 3/4 4/5 4/5 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1 1 1 1 1 1 1
ARITHMETIC AND LOGIC INSTRUCTIONS Rd Rd + Rr + C Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FFh - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF PC PC + k + 1 PC(15:0) Z, PC(21:16) 0 PC PC + k + 1 PC(15:0) Z, PC(21:16) 0 PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (I/O(A,b)=0) PC PC + 2 or 3 if (I/O(A,b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1
Subtract Immediate with Carry Logical AND Logical AND with Immediate Logical OR Logical OR with Immediate Exclusive OR One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set
BRANCH INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
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Mnemonics
BCLR SBI CBI BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH s
Operands
Flag Clear Set Bit in I/O Register Clear Bit in I/O Register A, b A, b Rr, b Rd, b
Description
SREG(s) 0 I/O(A, b) 1 I/O(A, b) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd K Rd (X)
Operation
Flags
SREG(s) None None T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1/2 2 2/3 1/2 2 2/3 1/2 2 2/3 1 1 1 2 1 1 2 1 1 2 1 1 1 2 2 1 1 1 1
Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Two's Complement Overflow. Clear Two's Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
DATA TRANSFER INSTRUCTIONS MOV LDI LD LD LD LD LD LD LD LD LD LDS ST ST ST ST ST ST ST ST ST STS IN OUT PUSH POP Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd, Z Rd, Z+ Rd, -Z Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Z, Rr Z+, Rr -Z, Rr k, Rr Rd, A A, Rr Rr Rd Copy Register Load Immediate Load Indirect Load Indirect and Post-Increment Load Indirect and Pre-Decrement Load Indirect Load Indirect and Post-Increment Load Indirect and Pre-Decrement Load Indirect Load Indirect and Post-Increment Load Indirect and Pre-Decrement Store Direct from SRAM Store Indirect Store Indirect and Post-Increment Store Indirect and Pre-Decrement Store Indirect Store Indirect and Post-Increment Store Indirect and Pre-Decrement Store Indirect Store Indirect and Post-Increment. Store Indirect and Pre-Decrement Store Direct to SRAM In from I/O Location Out to I/O Location Push Register on Stack Pop Register from Stack Break No Operation Sleep Watchdog Reset (see specific descr. for Sleep) (see specific descr. for WDR)
Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (k) Rr Rd I/O (A) I/O (A) Rr STACK Rr Rd STACK (see specific descr. for Break)
MCU CONTROL INSTRUCTIONS BREAK NOP SLEEP WDR
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ATtiny20
6. Ordering Information
6.1 ATtiny20
Speed (MHz) Power Supply Ordering Code(1) ATTINY20-SSU ATTINY20-SSUR ATtiny20-XU ATtiny20-XUR ATtiny20-CCU ATtiny20-CCUR ATtiny20-MMH(3) ATtiny20-MMHR(3) Package(2) 14S1 14S1 14X 14X 15CC1 15CC1 20M2 20M2 Operational Range
12
1.8 - 5.5V
Industrial (-40C to 85C)(4)
Notes:
1. Code indicators: - H: NiPdAu lead finish - U: matte tin - R: tape & reel 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). 3. Topside marking for ATtiny20: - 1st Line: T20 - 2nd Line: xx - 3rd Line: xxx 4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
Package Type 14S1 14X 15CC1 20M2 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14-lead, 4.4 mm Body, Thin Shrink Small Outline Package (TSSOP) 15-ball (4 x 4 Array), 0.65 mm Pitch, 3.0 x 3.0 x 0.6 mm, Ultra Thin, Fine-Pitch Ball Grid Array Package (UFBGA) 20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)
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7. Packaging Information
7.1 14S1
1
E E H
N
L
Top View
End View
e A1
b
SYMBOL
COMMON DIMENSIONS (Unit of Measure = mm/inches) MIN NOM MAX NOTE
A
1.35/0.0532 0.1/.0040 0.33/0.0130 8.55/0.3367 3.8/0.1497 5.8/0.2284 0.41/0.0160
- - - - - - - 1.27/0.050 BSC
1.75/0.0688 0.25/0.0098 0.5/0.0200 5 8.74/0.3444 3.99/0.1574 6.19/0.2440 1.27/0.0500 4 2 3
A
A1 b
D
D E
Side View
H L e
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-012, Variation AB for additional information. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. L is the length of the terminal for soldering to a substrate. 5. The lead width B, as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side.
2/5/02 TITLE
R
DRAWING NO. 14S1, 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14S1
2325 Orchard Parkway San Jose, CA 95131
REV. A
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ATtiny20
7.2 14X
Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AB-1.
INDEX MARK
PIN 1
4.50 (0.177) 6.50 (0.256) 4.30 (0.169) 6.25 (0.246)
5.10 (0.201) 4.90 (0.193)
1.20 (0.047) MAX
0.65 (.0256) BSC 0.30 (0.012) 0.19 (0.007)
0.15 (0.006) 0.05 (0.002)
SEATING PLANE
0~ 8
0.20 (0.008) 0.09 (0.004)
0.75 (0.030) 0.45 (0.018)
05/16/01 y 2325 Orchard Parkway San Jose, CA 95131 TITLE 14X (Formerly "14T"), 14-lead (4.4 mm Body) Thin Shrink Small Outline Package (TSSOP) . DRAWING NO. 14X . REV. B
R
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8235AS-AVR-03/10
7.3
15CC1
1
2
3
4 0.08
A Pin#1 ID B D C D b1 SIDE VIEW
A1 E TOP VIEW A A2
E1 e 15-Ob
D C D1 B A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = mm)
MIN NOM MAX NOTE
A A1 A2
- 0.05 0.25 0.25 2.90 2.90
- 0.010 0.43 REF 0.30 - 3.00 1.95 BSC 3.00 1.95 BSC 0.65 BSC
0.6 0.015 0.35 - 3.10 3.10 1 2
1 A1 Ball Corner
2
3
4
b b1 D D1 E E1
BOTTOM VIEW
e to the seating plane. Note2: Dimention "b1" is the solderable surface defined by the opening of the solder resist layer.
Note1: Dimention "b" is measured at the maximum ball dia. in a plane parallel
27/07/09 GPC CBC DRAWING NO. REV. B
TITLE Package Drawing Contact: 15CC1, 15-ball (4 x 4 Array), 3.0 x 3.0 x 0.6mm packagedrawings@atmel.com package, ball pitch 0.65mm,
Ultra thin, Fine-Pitch Ball Grid Array Package (UFBGA)
15CC1
14
ATtiny20
8235AS-AVR-03/10
ATtiny20
7.4 20M2
D
C y
Pin 1 ID
E
SIDE VIEW
TOP VIEW A1 A D2
16 17 18 19 20 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A 2 MIN 0.75 0.00 0.17 NOM 0.80 0.02 0.22 0.152 2.90 1.40 2.90 1.40 - 0.35 0.20 0.00 3.00 1.55 3.00 1.55 0.45 0.40 - - 3.10 1.70 3.10 1.70 - 0.45 - 0.08 MAX 0.85 0.05 0.27 NOTE
C0.18 (8X)
15 14
Pin #1 Chamfer (C 0.3)
1
e E2 13
12 11 3 4 5
A1 b C D D2 E
b
10 9 8 7 6
E2 e
L BOTTOM VIEW
K
0.3 Ref (4x)
L K y
10/24/08 Package Drawing Contact: packagedrawings@atmel.com GPC TITLE 20M2, 20-pad, 3 x 3 x 0.85 mm Body, Lead Pitch 0.45 mm, ZFC 1.55 x 1.55 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) DRAWING NO. 20M2 REV. B
15
8235AS-AVR-03/10
8. Errata
The revision letters in this section refer to the revision of the corresponding ATtiny20 device.
8.1
Rev. A
* Lock bits re-programming 1. Lock bits re-programming Attempt to re-program Lock bits to present, or lower protection level (tampering attempt), causes erroneously one, random line of Flash program memory to get erased. The Lock bits will not get changed, as they should not. Problem Fix / Workaround Do not attempt to re-program Lock bits to present, or lower protection level.
16
ATtiny20
8235AS-AVR-03/10
ATtiny20
9. Datasheet Revision History
9.1 Rev. 8235A - 03/10
1. Initial revision
17
8235AS-AVR-03/10
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8235AS-AVR-03/10

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